`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 2023/12/22 14:24:39
// Design Name: 
// Module Name: rv_regfile
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module rv_regfile(
    input CLK, input RST,

    //ISSUE_THREAD_ID --> rv_regfile
    input RS_THREAD_VALID,
    input [1:0] RS_THREAD_ID,
    //Inst-->rv_regfile
    input [4:0] RS1_INDEX,
    input [4:0] RS2_INDEX,

    //WB-->rv_regfile
    input [1:0] RD_THREAD_ID,
    input [4:0] RD_INDEX,
    input [31:0] RD_DIN,

    //rv_regfile-->decoder
    output [31:0] RS1_DOUT,
    output [31:0] RS2_DOUT
    );
    
    wire [31:0] rs1_dout,rs2_dout;
    wire rd_wr;
    assign rd_wr=(RD_INDEX==5'b0)?1'b0:1'b1;

    register_file_R2W1 #(32,7) REGFILE( 
        CLK,rd_wr,{RD_THREAD_ID,RD_INDEX},RD_DIN,
        {RS_THREAD_ID,RS1_INDEX},{RS_THREAD_ID,RS2_INDEX},
        rs1_dout,rs2_dout);
    
    wire [31:0] rs1_d0,rs2_d0;
    wire [4:0] rs1_index,rs2_index;
    regw #(.WIDTH(5)) RS1_INDEX_REG(CLK,RST,1'b1,RS1_INDEX,rs1_index);
    regw #(.WIDTH(5)) RS2_INDEX_REG(CLK,RST,1'b1,RS2_INDEX,rs2_index);

    regw #(.WIDTH(32)) RS1_REG(CLK,RST,1'b1,rs1_dout,rs1_d0);
    regw #(.WIDTH(32)) RS2_REG(CLK,RST,1'b1,rs2_dout,rs2_d0);
    assign RS1_DOUT=((rs1_index==5'b00000)|(RS_THREAD_VALID==1'b0))?32'b0:rs1_d0;
    assign RS2_DOUT=((rs2_index==5'b00000)|(RS_THREAD_VALID==1'b0))?32'b0:rs2_d0;

//      assign RS1_DOUT=((RS1_INDEX==5'b00000)|(RS_THREAD_VALID==1'b0))?32'b0:rs1_dout;
//      assign RS2_DOUT=((RS2_INDEX==5'b00000)|(RS_THREAD_VALID==1'b0))?32'b0:rs2_dout;

endmodule